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47
AT/TSC8x251G2D
4135F–8051–11/06
Table 40.
Bus Cycles AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
Notes: 1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2TOSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2NTOSC (N = 1..3).
Symbol
Parameter
12 MHz
16 MHz
Unit
Min
Max
Min
Max
TOSC
1/FOSC
83
62
ns
TLHLL
ALE Pulse Width
72
52
ns(2)
TAVLL
Address Valid to ALE Low
71
51
ns(2)
TLLAX
Address hold after ALE Low
14
6
ns
TRLRH(1) RD#/PSEN# Pulse Width
163
121
ns(3)
TWLWH WR# Pulse Width
165
124
ns(3)
TLLRL(1) ALE Low to RD#/PSEN# Low
17
11
ns
TLHAX
ALE High to Address Hold
90
57
ns(2)
TRLDV(1) RD#/PSEN# Low to Valid Data
133
92
ns(3)
TRHDX(1) Data Hold After RD#/PSEN# High
0
ns
TRHAX(1) Address Hold After RD#/PSEN# High
0
ns
TRLAZ(1) RD#/PSEN# Low to Address Float
0
ns
TRHDZ1 Instruction Float After RD#/PSEN# High
59
48
ns
TRHDZ2 Data Float After RD#/PSEN# High
225
175
ns
TRHLH1 RD#/PSEN# high to ALE High (Instruction)
60
47
ns
TRHLH2 RD#/PSEN# high to ALE High (Data)
226
172
ns
TWHLH
WR# High to ALE High
226
172
ns
TAVDV1 Address (P0) Valid to Valid Data In
289
160
ns(2)(3)
TAVDV2 Address (P2) Valid to Valid Data In
296
211
ns(2)(3)
TAVDV3 Address (P0) Valid to Valid Instruction In
144
98
ns(3)
TAXDX
Data Hold after Address Hold
0
ns
TAVRL(1) Address Valid to RD# Low
111
64
ns(2)
TAVWL1 Address (P0) Valid to WR# Low
111
64
ns(2)
TAVWL2 Address (P2) Valid to WR# Low
158
116
ns(2)
TWHQX Data Hold after WR# High
82
66
ns
TQVWH Data Valid to WR# High
135
103
ns(3)
TWHAX
WR# High to Address Hold
168
125
ns
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